Charge retention structures and techniques for implementing charge controlled resistors in memory cells and arrays of memory

A memory cell comprising:

• a charge-controlled resistor (“CCR”) including:
• a first doped portion of a silicon carbide structure configured to include a charge cloud;
• a second doped portion of the silicon carbide structure formed adjacent to the first doped portion of the silicon carbide structure to establish a barrier for charge carriers;
• a dielectric material coupled to at least the first doped portion of the silicon carbide structure;
• and
• a resistive element formed adjacent to the dielectric material,
• wherein the size of the charge cloud is configured to establish a degree of resistance of the resistive element.

A memory array comprising:

• a plurality of memory cells including charge-controlled resistors (“CCRs”) in a plane, each charge-controlled resistor including a silicon carbide-based PNP diode formed on a silicon substrate;
• a plurality of charge clouds in the charge-controlled resistors;
• a plurality of word lines formed in between the plane and the silicon substrate in which a word line is a p-type silicon carbide portion of the silicon carbide-based PNP diode;
• a plurality of bit lines formed in another plane and configured to couple to first terminals of the charge-controlled resistors;
• and
• a plurality of source lines formed in yet another plane and configured to couple to second terminals of the charge-controlled resistor,
• wherein potential differences applied to the plurality of bit lines and the plurality of source lines modify amounts of charge carriers for the plurality of charge clouds.