Snap-back tolerant integrated circuits
AssigneeAtmel Corporation
InventorPhilip S. Ng
Life of this patent
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Abstract
A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON) state. An auxiliary circuit coupled to a source node of the first NMOS transistor may be configured to provide a bias potential at the source node of the first NMOS transistor, when the first NMOS transistor is in a non-conducting state (OFF).
Claims14
A method for preventing snap-back current in a circuit including a first N-channel MOS (NMOS) transistor having an associated parasitic bipolar transistor, the method comprising:
- connecting a second NMOS transistor in series with the first NMOS transistor;
- coupling a gate node of the second NMOS transistor to a bias node, such that a the second NMOS transistor is in a conductive state;
- and
- coupling a source node of the first NMOS transistor to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), the bias potential preventing the associated parasitic bipolar transistor from turning on.
A snap-back tolerant circuit comprising:
- a first NMOS transistor having an associated parasitic bipolar transistor, a source node of the first NMOS transistor being coupled to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source node of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), the bias potential preventing the associated parasitic bipolar transistor from turning on;
- and
- a second NMOS transistor in series with the first NMOS transistor, the source node of the second NMOS transistor being coupled to the drain node of the first NMOS transistor, a gate node of the second NMOS transistor being coupled to a bias node, such that the second NMOS transistor is conductive.
A snap-back tolerant driver comprising:
- a level shifter circuit configured to provide a high voltage at an output node;
- and
- an inverter circuit having an input node coupled to the output node, at least one of the level shifter circuit and the inverter circuit including:
- a first NMOS transistor having an associated parasitic bipolar transistor, a source node of the first NMOS transistor being coupled to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source node of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), the bias potential preventing the associated parasitic bipolar transistor from turning on;
- and
- a second NMOS transistor in series with the first NMOS transistor, the source node of the second NMOS transistor being coupled to the drain node of the first NMOS transistor, a gate node of the second NMOS transistor being coupled to a bias node, such the second NMOS transistor is conductive.
A memory device comprising:
- a high voltage multiplier module;
- a level shifter circuit configured to provide a high voltage at an output node;
- and
- an inverter circuit having an input node coupled to the output node, at least one of the level shifter circuit and the inverter circuits including:
- a first NMOS transistor having an associated parasitic bipolar transistor, a source node of the first NMOS transistor being coupled to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source node of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), the bias potential preventing the associated parasitic bipolar transistor from turning on;
- and
- a second NMOS transistor in series with the first NMOS transistor, a drain node of the second NMOS transistor being coupled to an output node and the source node of the second NMOS transistor being coupled to the drain node of the first NMOS transistor, a gate node of the second NMOS transistor being coupled to a bias node, such that that the second NMOS transistor is in conductive (ON) state.
Dependencies are inferred from the claim text.