Ethernet system

Apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, the apparatus comprising:

• an analog to digital converter arranged to convert the first discrete analog signal level to a corresponding digital first information signal, to convert the second discrete analog signal level to a corresponding digital second information signal, to convert the third discrete analog signal level to a corresponding digital third information signal, to convert the fourth analog signal level to a corresponding digital fourth information signal, to convert the fifth discrete analog signal level to a corresponding digital fifth information signal, to convert the sixth discrete analog signal level to a corresponding digital sixth information signal, to convert the seventh discrete analog signal level to a corresponding digital seventh information signal, to convert the eighth discrete analog signal level to a corresponding digital eighth information signal and to convert the ninth discrete analog signal level to a corresponding digital ninth information signal;
• and
• circuitry arranged to individually identify each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels, to shift in time the first information signal relative to the first discrete analog signal level, to shift in time the second information signal relative to the second discrete analog signal level, to shift in time the third information signal relative to the third discrete analog signal level, to shift in time the fourth information signal relative to the fourth discrete analog signal level, to shift in time the fifth information signal relative to the fifth discrete analog signal level, to shift in time the sixth information signal relative to the sixth discrete analog signal level, to shift in time the seventh information signal relative to the seventh discrete analog signal level, to shift in time the eighth information signal relative to the eighth discrete analog signal level and to shift in time the ninth information signal relative to the ninth discrete analog signal level.

In apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, a method of processing the received discrete analog signal levels comprising:

• converting the first discrete analog signal level to a corresponding digital first information signal;
• converting the second discrete analog signal level to a corresponding digital second information signal;
• converting the third discrete analog signal level to a corresponding digital third information signal;
• converting the fourth discrete analog signal level to a corresponding digital fourth information signal;
• converting the fifth discrete analog signal level to a corresponding digital fifth information signal;
• converting the sixth discrete analog signal level to a corresponding digital sixth information signal;
• converting the seventh discrete analog signal level to a corresponding digital seventh information signal;
• converting the eighth discrete analog signal level to a corresponding digital eighth information signal;
• converting the ninth discrete analog signal level to a corresponding digital ninth information signal;
• individually identifying each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels;
• shifting in time the first information signal relative to the first discrete analog signal level;
• shifting in time the second information signal relative to the second discrete analog signal level;
• shifting in time the third information signal relative to the third discrete analog signal level;
• shifting in time the fourth information signal relative to the fourth discrete analog signal level;
• shifting in time the fifth information signal relative to the fifth discrete analog signal level;
• shifting in time the sixth information signal relative to the sixth discrete analog signal level;
• shifting in time the seventh information signal relative to the seventh discrete analog signal level;
• shifting in time the eighth information signal relative to the eighth discrete analog signal level;
• and
• shifting in time the ninth information signal relative to the ninth discrete analog signal level.

A communication system for decoding signals having three or more analog signal levels to represent information transmitted by a first computer over a plurality of pairs of twisted wires to a second computer, said communication system including a transceiver comprising:

• a plurality of receivers and transmitters operatively coupled to respective ones of said plurality of said pairs of twisted wires, wherein each of said plurality of receivers comprises:
• an analog to digital converter;
• an automatic gain control circuit;
• and
• a digital adaptive equalizer that includes a feed forward equalizer, a decision feedback equalizer and a data slicer,
• wherein each of said analog to digital converters sampling said analog signal at a sampling rate, each of said automatic gain control circuits receiving said analog signal from one of said pairs of twisted wires and providing gain control at the input to a respective one of said analog to digital converters, and each of said equalizers producing recovered digital data from said sampled analog signal provided at the input of said equalizer, and
• wherein said transceiver includes a plurality of transmitters that simultaneously transmit three or more analog signal levels to said first computer over said plurality of pairs of twisted wires.

A computer network device, comprising:

• transmitting circuitry including an encoder and data splitter circuitry, a first transmitter, a second transmitter and a third transmitter, wherein the first transmitter, the second transmitter and the third transmitter are coupled to a network via a respective pair of twisted wires;
• receiving circuitry including clock recover circuitry, data combiner and decoder circuitry, a first receiver and equalizer, a second receiver and equalizer and a third receiver and equalizer, wherein the clock recover circuitry is disposed along a data path between the receivers and equalizers and the data combiner and decoder circuitry, wherein the first receiver and equalizer, the second receiver and equalizer and the third receiver and equalizer is coupled to the network via a respective pair of twisted wires;
• a media access control coupled to a system bus, the encoder and data splitter circuitry of the transmitting circuitry and the data combiner and decoder circuitry of the receiver circuitry;
• and
• collision detect and link control circuitry coupled to the media access control, the transmitters and the receivers and equalizers,
• wherein the first receiver and equalizer comprises an automatic gain control stage, an analog-to-digital converter and a digital adaptive equalizer, wherein the automatic gain control state is coupled to the analog-to-digital converter, and wherein the analog-to-digital converter is coupled to the digital adaptive equalizer.