Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains

A delay circuit, comprising:

• a plurality of voltage domains;
• a plurality of paths;
• wherein each of the plurality of paths traverses a portion of the plurality of voltage domains and has a delay responsive to at least one of the plurality of voltage domains;
• and
• a means for producing a delay output related to the delay of the plurality of paths.

A method of producing a delay output in a delay circuit, comprising:

• receiving a plurality of signals from a plurality of paths traversing a portion of a plurality of voltage domains, wherein the plurality of paths has a delay response to at least one of the plurality of voltage domains;
• delaying each of the plurality of signals related to the delay of a corresponding path of the plurality of paths;
• and
• generating a delay output from a delay circuit receiving the plurality of signals.

A memory system, comprising:

• a control system;
• a plurality of voltage domains;
• a sense path traversing a first portion of the plurality of voltage domains and having a first delay responsive to the first portion;
• an access path traversing a second portion of the plurality of voltage domains having a second delay responsive to the second portion;
• and
• a delay circuit coupled to the sense path and configured to produce a delay output related to the first and second delays.