Quad flat no lead (qfn) integrated circuit (ic) package having a modified paddle and method for designing the package
AssigneeAgere Systems Inc.
InventorsLawrence Wayne Golick, Scott E. Hynes, Thomas J. Pllyer
Life of this patent
Estimating the term…
Abstract
A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle as necessary or desired in order to facilitate routing and/or via placement, the overall size of the PWB or PCB can be reduced without sacrificing the thermal or electrical performance advantages that the paddle provides. In addition, the reduction in the overall size of the PWB or PCB results in reduced cost.
Claims33
A Quad Flat No Lead (QFN) integrated circuit (IC) package comprising:
- a leadframe comprising one or more electrically conductive lands and an electrically and thermally conductive paddle, the paddle having an exposed portion and an unexposed portion, the unexposed portion of the paddle having a top surface having a width in an X dimension and a length in a Y dimension, the top surface of the unexposed portion having an area equal to the width of the top surface of the unexposed portion times the length of the top surface of the unexposed portion, the bottom surface of the exposed portion of the paddle having a width in the X dimension and a length in the Y dimension, the bottom surface of the exposed portion having an area equal to the width of the bottom surface of the exposed portion of the paddle times the length of the bottom surface of the exposed portion;
- a die having a bottom surface attached to the top surface of the unexposed portion of the paddle, the die having a width in an X dimension and a length in a Y dimension, the bottom surface of the die having an area equal to the width of the die times the length of the die;
- an encasement that at least partially encases the leadframe and the die, the lands having ends that are exposed through the encasement and that are substantially flush with the encasement, the bottom surface of the exposed portion of the paddle being exposed through the encasement and substantially flush with the encasement;
- and
- wherein the area of the bottom surface of the exposed portion of the paddle is smaller than the area of the top surface of the unexposed portion of the paddle.
A method for designing a Quad Flat No Lead (QFN) integrated circuit (IC) package comprising:
- receiving information about a configuration of a printed wiring board (PWB) or printed circuit board (PCB) on which the IC package is intended to be mounted;
- creating a paddle configuration for a leadframe of the IC package based on the information about the configuration of the PWB or PCB, the paddle having an exposed portion and an unexposed portion, the unexposed portion of the paddle having a top surface for attaching a bottom surface of a die to the paddle, the top surface of the unexposed portion having a width in an X dimension and a length in a Y dimension, the top surface of the unexposed portion having an area equal to the width of the top surface of the unexposed portion times the length of the top surface of the unexposed portion, the bottom surface of the exposed portion of the paddle having a width in the X dimension and a length in the Y dimension, the bottom surface of the exposed portion having an area equal to the width of the bottom surface of the exposed portion of the paddle times the length of the bottom surface of the exposed portion;
- determining whether the leadframe having the paddle configuration meets leadframe manufacturability constraints;
- determining whether a QFN IC package comprising the leadframe having the paddle configuration meets IC package manufacturability constraints;
- and
- determining whether a QFN IC package comprising the leadframe having the paddle configuration meets heat dissipation constraints.
A leadframe for Quad Flat No Lead (QFN) integrated circuit (IC) package, the leadframe comprising:
- one or more electrically conductive lands;
- and
- an electrically and thermally conductive paddle, the paddle having an exposed bottom surface for attachment to a printed circuit or printed wiring board and having an unexposed top surface for attachment to a bottom surface of a die, the exposed bottom surface of the paddle being smaller in area than the exposed top surface of the paddle.
A method for designing a leadframe for Quad Flat No Lead (QFN) integrated circuit (IC) package, the method comprising:
- selecting a leadframe design having a paddle with a bottom exposed surface for attachment to a printed circuit board or printed wiring board that is smaller in area than a top surface of an exposed portion of the paddle.
Dependencies are inferred from the claim text.