Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device

A complementary metal-oxide-semiconductor (CMOS) device, comprising:

• a semiconductor substrate comprising a P type metal-oxide-semiconductor (PMOS) region and an N type metal-oxide-semiconductor (NMOS) region;
• a first gate dielectric layer and a second gate dielectric layer on the semiconductor substrate;
• and
• a first gate structure and a second gate structure on the first gate dielectric layer and the second gate dielectric layer, respectively;
• wherein the first gate dielectric layer and the underlying semiconductor substrate together comprises a first dopant of a first concentration, the second gate dielectric layer and the underlying semiconductor substrate together comprises a second dopant of a second concentration, the first dopant and the second dopant each are dependently at least one selected from the group consisting of fluorine ion and carbon ion;
• and the first concentration and the second concentration are different.