Semiconductor device and manufacturing method thereof
AssigneeElpida Memory, Inc.
InventorTomohiro KADOYA
Life of this patent
Estimating the term…
Abstract
A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.
Claims15
A semiconductor device comprising a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein:
- lower electrodes of capacitors included in the memory cell are at least supported at a portion of an outer side face thereof by a support film;
- the support film is formed as a pattern combining a first support pattern linearly extending in a first direction and a second support pattern linearly extending in a second direction that crosses to the first direction;
- the intervals of the first and second support patterns are both equal to or greater than 1.5F;
- and
- the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.
A semiconductor device comprising:
- a memory cell region including a plurality of memory cells, each of the memory cells having a capacitor belonging to a first group or a second group;
- and
- a support film to hold lower electrodes of the capacitors, the support film having a plurality of openings formed by removing a part of the support film, wherein
- each of the memory cells is disposed in the memory cell region by 6F2 layout whose size is defined by a numerical value of a design rule F, each of the capacitors belonging to the first group exposes a part of an outer side face of the lower electrode to the opening of the support film, and each of the capacitors belonging to the second group dose not expose an outer side face of the lower electrode to the opening of the support film.
A method of manufacturing a semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, the method comprising:
- forming a support film on a sacrificial interlayer film;
- forming a capacitor hole penetrating the support film and the sacrificial interlayer film;
- forming a lower electrode of a capacitor inside the capacitor hole;
- patterning the support film so as to have a pattern combining a first support pattern linearly extending in a first direction and a second support pattern linearly extending in a second direction that crosses to the first direction, the intervals of the first and second support patterns both equal to or greater than 1.5F, and the interval of one of the first and second support patterns greater than the interval of the other one of the first and second support patterns;
- and
- selectively removing the sacrificial interlayer film via an opening formed between patterns of the support film.
Dependencies are inferred from the claim text.