Semiconductor integrated circuit device
AssigneeRenesas Technology Corp.
InventorHiroharu SHIMIZU
Life of this patent
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Abstract
A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].
Claims12
A semiconductor integrated circuit device comprising:
- a first tap for the supply of a first potential, the first tap being formed in a first direction;
- a second tap for the supply of a second potential, the second tap being formed in the first direction and positioned so as to confront the first tap in a second direction intersecting the first direction;
- a cell array comprising a plurality of standard cells each formed between the center of the first tap in the second direction and the center of the second tap in the second direction;
- and
- a plurality of layers of wiring lines formed over the first tap, the second tap and the cell array,
- wherein a cell height between the first and second taps is set to [(an integer+0.5)×a wiring pitch of the second-layer wiring lines out of the plural layers of wiring lines].
A semiconductor integrated circuit device comprising:
- a first tap for the supply of a first potential, the first tap being formed in a first direction;
- a second tap for the supply of a second potential, the second tap being formed in the first direction and positioned so as to confront the first tap in a second direction intersecting the first direction;
- a cell array comprising a plurality of standard cells each formed between the center of the first tap in the second direction and the center of the second tap in the second direction;
- and
- a plurality of layers of wiring lines formed over the first tap, the second tap and the cell array,
- wherein a cell height between the first and second taps is set to [(an integer+0.25)×a wiring pitch of the second-layer wiring lines out of the plural layers of wiring lines].
Dependencies are inferred from the claim text.