Configurable hierarchical comma-free reed-solomon decoding circuit and method thereof
AssigneeNational Chung Cheng University
InventorsYuan-Sun CHU, Yi-Ren CHEN, Chia-Ying HUANG, Chi-Fang LI
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AssigneeNational Chung Cheng University
InventorsYuan-Sun CHU, Yi-Ren CHEN, Chia-Ying HUANG, Chi-Fang LI
Estimating the term…
The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.
A configurable hierarchical comma-free Reed-Solomon decoding circuit comprising:
A method for configurablizing a hierarchical comma-free Reed-Solomon decoding circuit comprises steps:
Dependencies are inferred from the claim text.