Test generation methods for reducing power dissipation and supply currents

One or more computer-readable media storing computer-executable instructions which when executed by a computer cause the computer to perform a method of generating test patterns for testing an integrated circuit, the method comprising:

• determining hold probabilities for state elements of a circuit design, the hold probability for a respective state element indicating the probability that the respective state element will output the same logic value during two or more consecutive clock cycles;
• generating a test cube targeting one or more faults in the circuit design, the test cube initially comprising specified values that target the one or more faults and further comprising unspecified values;
• and
• modifying the test cube by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities.

One or more computer-readable media storing computer-executable instructions which when executed by a computer cause the computer to perform a method of generating test patterns for testing an integrated circuit design, comprising:

• selecting one or more faults to target from a fault list;
• generating a first set of test pattern values that target the one or more selected faults;
• generating a second set of test pattern values that reduces power consumption in the integrated circuit design during testing, the second set of test pattern values being determined at least in part from probability values indicating whether one or more state elements in the integrated circuit design will output constant logic values over two or more consecutive clock cycles;
• and
• storing a test pattern comprising at least the first set of test pattern values and the second set of test pattern values.

One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method of generating test patterns for testing an integrated circuit, comprising:

• generating a test cube targeting one or more faults in a circuit design, the test cube initially comprising specified values that target the one or more faults and unspecified values;
• simulating application of the test cube to the circuit design;
• identifying one or more logic gate outputs or state elements that have a respective known value in a first time frame and an unknown value in a second time frame, the first time frame and the second time frame being consecutive time frames;
• and
• expanding the test cube by specifying one or more of the unspecified values in the test cube with values that cause one or more of the identified logic gate outputs or state elements to have the respective known value during both the first time frame and the second time frame.

A system, comprising:

• means for determining hold probabilities for state elements of a circuit design, the hold probability for a respective state element indicating the probability that the respective state element will output the same logic value during two or more consecutive clock cycles;
• means for generating a test cube targeting one or more faults in the circuit design, the test cube initially comprising specified values that target the one or more faults and further comprising unspecified values;
• and
• means for modifying the test cube by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities.

A system, comprising:

• means for selecting one or more faults to target from a fault list;
• means for generating a first set of test pattern values that target the one or more selected faults;
• means for generating a second set of test pattern values that reduces power consumption in the integrated circuit design during testing, the second set of test pattern values being determined at least in part from probability values indicating whether one or more state elements in the integrated circuit design will output constant logic values over two or more consecutive clock cycles;
• and
• means for storing a test pattern comprising at least the first set of test pattern values and the second set of test pattern values.

A system, comprising:

• means for generating a test cube targeting one or more faults in a circuit design, the test cube initially comprising specified values that target the one or more faults and unspecified values;
• means for simulating application of the test cube to the circuit design;
• means for identifying one or more logic gate outputs or state elements that have a respective known value in a first time frame and an unknown value in a second time frame, the first time frame and the second time frame being consecutive time frames;
• and
• means for expanding the test cube by specifying one or more of the unspecified values in the test cube with values that cause one or more of the identified logic gate outputs or state elements to have the respective known value during both the first time frame and the second time frame.