Software Selectable Adjustment of SIMD Parallelism

A SIMD data processor, comprising:

• a first processing element responsive to program instructions, for processing data of a first width;
• a second processing element responsive to program instructions, connected to operate in parallel with the first processing unit, the parallel operation of the first and second processing elements providing SIMD processing of data of a second width greater than the first width, wherein the combination of said first and second processing elements are configured to process data in response to SIMD type instructions;
• control logic for selectively activating and deactivating the second processing element in response to setting of a mode by program instructions calling for processing of data of the second width and calling for processing of data of the first width, respectively;
• and
• an instruction expansion stage configured to convert a SIMD instruction calling for processing of data of the second width to a plurality of instructions calling for processing of data of the first width and configured to supply the expanded plurality of instructions sequentially to the first processing element for execution, when the second processing element has been deactivated.

A method of processing a SIMD instruction in a SIMD data processor when a width of a data path required by the SIMD instruction is greater than a width of an active data path, comprising:

• receiving a SIMD instruction requiring a data path width greater than the width of the active data path;
• expanding the SIMD instruction into two or more instructions in response to the received SIMD instruction requiring a data path width greater than the width of the active data path, wherein each expanded instruction requires at most the width of the active data path;
• and
• sequentially processing the two or more expanded instructions utilizing the active data path.

A SIMD data processor, comprising:

• a first processing means having a first data path width;
• a second processing means connected to operate in parallel with the first processing means, the parallel operation of the first and second processing means providing a second data path width greater than the first data path width;
• means for activating the second processing means in response to an instruction calling for processing of data of the second width and for deactivating the second processing means in response to an instruction calling for processing of data of the first width;
• and
• expansion means for converting an instruction calling for processing of data of the second width to a plurality of instructions calling for processing of data of the first width when the second processing means has been deactivated and supplying the plurality of instructions sequentially to the first arithmetic logic unit for execution.