Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips

A common memory controller capable of controlling chips including a respective memory among different types of memories operating with different specifications, comprising:

• a first interface portion that receives a control output signal to access the chips from a controller, and outputs a control input signal to the controller;
• a second interface portion that outputs a memory input signal through a common bus terminal portion coupled to the chips and receives a memory output signal through the common bus terminal portion;
• an operation memory portion that outputs a first control signal including specifications of the memories;
• an arbiter that outputs a second control signal and a third control signal;
• a conversion control portion that converts the control output signal into the memory input signal in response to at least one of the first control signal and the second control signal, and converts the memory output signal respectively into the control input signal;
• and
• a signal holder that holds the control output signals in response to at least one of the third control signal and a fourth control signal from the conversion control portion,
• wherein the the memory input signal includes a first memory input signal corresponding to a first memory and a second memory input signal corresponding to a second memory, type of which is different from the type of the first memory.

A memory system comprising:

• a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
• a controller for outputting controller output signals to access the memory chips;
• a memory controller for converting the controller output signals into memory input signals according to operation specifications of the respective memory chips, and converting memory output signals output from the memory chips into controller input signals receivable to the controller;
• and
• a common bus for coupling to the first chip, the second chip and the memory controller to transmit the memory input signals and the memory output signals corresponding to a control signal,
• wherein the command specifications for the first chip and the second chip are different so that the memory input signals of the first chip and the second chip are different,
• wherein the memory controller includes an arbiter for outputting a instruction signal and a signal holding unit for temporarily holding the controller output signals in response to the instruction signal for operating one of the chips during the controller operation of another one of the chips, and an operation of the one of the chips is performed after the controller operation of another one of the chips.