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US 2010/0146156 A1Published application
Memory control apparatus and method
AssigneeCanon Kabushiki Kaisha
InventorToshiaki Minami
Life of this patent
Estimating the term…
Abstract
A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request source. The plurality of memory access requests are executed by time division and concurrently.
Claims13
-11. (canceled)
A memory control apparatus comprising:
- read means for reading data from a memory in accordance with a plurality of read requests from a plurality of request sources;
- storage means for storing the read data;
- and
- transfer means for transferring the read data from said storage means to the plurality of request sources in accordance with priority set for the plurality of request sources, such that data transfer to a first request source is interrupted and the read data is transferred to a second request source if a) the read data to be transferred to the second request source is stored by said storage means while said transfer means transfers the read data to the first request source, and b) the first request source is set to a priority lower than that set to the second request source.
1 more element
A memory control method comprising the steps of:
- reading data from a memory in accordance with a plurality of read requests from a plurality of request sources;
- storing the read data;
- and
- transferring the stored read data to the plurality of request sources in accordance with priority set for the plurality of request sources, such that data transfer to a first request source is interrupted and the read data is transferred to a second request source if a) the read data to be transferred to the second request source is stored by a storage means while a transfer means transfers the read data to the first request source, and b) the first request source is set to a priority lower than that set to the second request source.
1 more element
An embedded equipment having a memory, a system bus, and a memory controller,
- said memory controller comprising a buffer for temporarily storing data read from said memory in accordance with a plurality of read requests from a plurality of request sources, and transferring the read data from said buffer means to the plurality of request sources in accordance with priority set for the plurality of request sources, such that data transfer to a first request source is interrupted and the read data is transferred to a second request source if a) the read data to be transferred to the second request source is stored by a storage means while a transfer means transfers the read data to the first request source, and b) the first request source is set to a priority lower than that set to the second request source.
Dependencies are inferred from the claim text.