Digital filter, its synthesizing device, synthesizing program and synthesizing program recording medium

A digital filter comprising:

• a shift register receiving two signals and having two groups of a plurality of registers for storing data, the shift register shifting data in the plurality of registers of each of the two groups every sample;
• a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and two groups of a plurality of output signals of the shift register, multiplying the two groups of the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and outputting the summed result to the shift register as the first input, and also determining whether or not round-up is involved in rounding processing from the summed result obtained by multiplying the two groups of the plurality of output signals of the shift register by respective coefficients and summing all of the multiplied results and the input signal, and outputting the determined result to the shift register as the second input;
• a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.

A digital filter synthesizing device for synthesizing a digital filter from:

• a shift register having a plurality of registers for storing data, the shift register shifting data in the plurality of registers every sample;
• a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and supplying the summed result to the shift register;
• and
• a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.

A digital filter synthesizing program for allowing a computer to synthesize a digital filter, comprising the steps of:

• synthesizing a shift register having a plurality of registers for storing data, the shift register shifting data in the plurality of registers every sample;
• synthesizing a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and supplying the summed result to the shift register;
• and
• synthesizing a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.