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US 2010/0142660 A1Published application
Digital frequency locked delay line
AssigneeMicron Technology, Inc.
InventorCurt Schnarr
Life of this patent
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Abstract
A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
Claims27
A device comprising:
- a first selector including a first input node for receiving a clock signal, a second input node for receiving a preamble enable signal, and an selector output node;
- a delay line including a delay input node coupled to the selector output node, a delay output node, and a number of delay cells coupled between the delay input node and the delay output node, wherein each of the cells includes a cell output node, and a number of delay control nodes for receiving a delay code;
- a delay controller including a first input node coupled to the delay input node, a second input node coupled to the delay output node, and a select node coupled to the first selector;
- and
- a second selector including an output node and number of input nodes, each of the input nodes coupled to the cell output node of one of the delay cells.
2 more elements
A device comprising:
- a number of variable delay cells coupled in series with a delay input node for receiving an input signal and coupled to a delay output node for providing a delayed output signal, each of the delay cells including a cell output node for providing a cell output signal, each of the delay cells also including a number of delay control node for receiving a digital control code;
- a phase detector including a first input node coupled to the delay input node, and a second input node coupled to the delay output node;
- a counter including a number of counter bit lines coupled to the delay control nodes, and a number of input nodes responsive to the phase detector for adjusting a count value on the counter bit lines;
- and
- a selector coupled to the cell output node of at least two of the delay cells for selecting the cell output node from one of the delay cells to provide an enable signal.
2 more elements
A method comprising:
- setting a delay code to a number of delay cells of a delay line;
- propagating an input signal through the delay cells to obtain a delayed output signal;
- adjusting the delayed output signal until the input signal and the delayed output signal have a fixed signal relationship;
- selecting among multiple cell output signals at multiple cell output nodes of the delay cells a selected cell output signal;
- and
- passing the selected cell output signal to an enable node.
3 more elements
A method comprising:
- receiving at least one data signal at an input node of a data receiver;
- receiving at least one strobe signal at an input node of a strobe receiver, wherein the strobe signal carries timing information of the data signal;
- propagating an input signal through a number of variable delay cells to obtain a plurality of cell output signals in which each of the cell output signals has a fixed signal relationship with the input signal;
- selecting one of the plurality of cell output signals to be an enable signal;
- and
- sending the enable signal to at least one of the data receiver and strobe receiver to pass at least one of the strobe signal and the data signal from the input node of at least one of the data receiver and strobe receiver to an output node of at least one of the data receiver and strobe receiver.
3 more elements
Dependencies are inferred from the claim text.