US 2010/0142278 A1 · PAGE BUFFER CIRCUIT, NONVOLATILE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE

Abstract

A page buffer circuit comprises a sense unit, a latch unit, and a bit line voltage control unit. The sense unit is configured to couple a bit line and a sense node in response to a sense control signal in response to the sense control signal. The latch unit includes a plurality of latch circuits configured to latch data programmed or to be programmed. The bit line voltage control unit is configured to classify program states of memory cells, coupled to the selected bit line, into first to nth groups by performing first to nth verification operations after a first program operation of a program operation and is configured to control a voltage level of the sense control signal in order to transfer a bit line voltage to the selected bit line.

Claims20

Dependent claims

A page buffer circuit, comprising:

a sense unit configured to couple a bit line and a sense node in response to a sense control signal to detect a voltage of the selected bit line or transfer a voltage of the sense node to the selected bit line;
a latch unit comprising a plurality of latch circuits that are configured to latch data to be programmed into a memory cell or that are coupled to the sense node in order to store data programmed into a memory cell;
and
a bit line voltage control unit coupled to the selected bit line and configured to classify program states of memory cells into first to nth groups by performing first to nth verification operations after a first program operation of a program operation and further configured to control a voltage level of the sense control signal in order to transfer a bit line voltage to the selected bit line, where n is an integer greater than one.

1 more element

A nonvolatile memory device, comprising:

a memory cell array comprising a number of memory blocks each including memory cells for storing data, the memory cells being coupled by a bit line and a word line;
and
a page buffer unit coupled to the bit line and configured to include page buffers each comprising a plurality of latch circuits, wherein the latch circuits are configured to latch data to be programmed into a memory cell or store data programmed into a memory cell, and each of the page buffers is configured to classify memory cells into first to nth groups according to a program degree of each memory cell by performing first to nth verification operations upon a verification operation subsequent to a program operation according to a first program pulse and is configured to precharge a bit line to a voltage set on a group basis, wherein n is an integer greater than one.

A method of operating a nonvolatile memory device, comprising:

a step of performing a first program operation by applying a first program pulse to a selected word line with;
a bit line group classification step of performing first to nth verification operations using respective first to nth verification voltages, in performing a verification operation for the first program operation, and classifying bit lines into first to nth groups according to each of the verification results;
a step of setting a bit line voltage to each of the classified first to nth groups;
a second program and verification step of, before performing a program operation according to a second program pulse, precharging a bit line, corresponding to each of the groups, to the set bit line voltage, performing a second program operation, and performing a verification operation using the nth verification voltage;
and
an nth program and verification step of, if a result of an (n−1)th program and verification step is not a program pass, before performing a program operation according to an (n−1)th program pulse, gradually raising a bit line voltage corresponding to each of the groups by a first voltage, precharging a bit line to the raised bit line voltage, performing an nth program operation, and performing a verification operation using an nth verification voltage, wherein n is an integer greater than one.

3 more elements

Dependencies are inferred from the claim text.

Page buffer circuit, nonvolatile device including the same, and method of operating the nonvolatile memory device

Life of this patent

Page buffer circuit, nonvolatile device including the same, and method of operating the nonvolatile memory device

Life of this patent

Abstract

Claims20