Semiconductor storage device

A semiconductor storage device designed using a vertical transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a pillar-shaped silicon layer, and a gate electrode is formed to surround the pillar-shaped silicon layer, characterized by comprising a memory cell array formed with a plurality of first bit lines each comprised of a first layer and connected to a sense amplifier, and a plurality of second bit lines each comprised of a different layer from the first layer and connected to the sense amplifier, each of the second bit lines having a lower resistance than that of the first bit line, wherein a plurality of the vertical transistors are formed on each of the first bit lines, in a row, in such a manner as to allow the gate electrodes of the vertical transistors to serve as respective ones of a plurality of word lines each wired in a direction perpendicular to a corresponding one of the first bit lines, and wherein each of the vertical transistors includes a first transistor for selecting an associated one of the memory cells, and a second transistor for connecting corresponding ones of the first bit lines and the second bit lines, and wherein the second transistor is adapted to be kept in its ON state during an operation of the storage device, whereby each of the first bit lines is backed with the corresponding one of the second bit lines to allow the first and second bit lines to form a substantially low-resistance bit line.