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US 2010/0141492 A1Published application
Low power consumption analog-to-digital converter
AssigneeIndustrial Technology Research Institute
InventorsKuan-Yu Lin, Tsung-Shuen Hung
Life of this patent
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Abstract
A low power consumption analog-to-digital converter (ADC) is provided. The switched capacitor circuit and the operational amplifier of the pipelined stage within the present low power consumption ADC are designed to close loop, and the operational amplifier is operated at the incomplete settling of the linear settling, namely, the operational amplifier is not operated at the slew state. Therefore, the pipelined stage would not produce signal dependent distortion, such that the gain error produced by the operational amplifier could be seen as a constant gain error.
Claims21
An analog-to-digital converter (ADC), comprising:
- a first pipelined stage, for receiving and converting a sampled and held direct-current voltage so as to output a first digital code and a first residue voltage;
- and
- a second pipelined stage, for receiving and converting the first residue voltage so as to output a second digital code and a second residue voltage, wherein both of the first and the second pipelined stages comprise:
- a switched capacitor circuit;
- and
- an operational amplifier, constituting a closed-loop with the switched capacitor circuit, and operating in an incomplete settling of a linear settling;
- and
- a flash ADC, coupled to the second pipelined stage, for receiving and converting the second residue voltage so as to output a third digital code;
- a combination unit, coupled to the first and the second pipelined stages and the flash ADC, for receiving and combining the first, the second and the third digital codes so as to output an original digital signal;
- and
- a digital background calibration unit, coupled to the combination unit, the first and the second pipelined stages and the flash ADC, for receiving the original digital signal and the first, the second and the third digital codes, and calibrating the original digital signal according to a reference digital signal and the first, the second and the third digital codes, so as to output an accuracy digital signal.
8 more elements
An analog-to-digital converter (ADC), comprising:
- a pipelined stage, for receiving and converting a sampled and held direct-current voltage so as to output a first digital code and a residue voltage, wherein the pipelined stage comprises:
- a switched capacitor circuit;
- and
- an operational amplifier, constituting a closed-loop with the switched capacitor circuit, and operating in an incomplete settling of a linear settling;
- and
- a flash ADC, coupled to the pipelined stage, for receiving and converting the residue voltage so as to output a second digital code;
- a combination unit, coupled to the pipelined stage and the flash ADC, for receiving and combining the first and the second digital codes so as to output an original digital signal;
- and
- a digital background calibration unit, coupled to the combination unit, the pipelined stage and the flash ADC, for receiving the original digital signal and the first and the second digital codes, and calibrating the original digital signal according to a reference digital signal and the first and the second digital codes, so as to output an accuracy digital signal.
6 more elements
An analog-to-digital converter (ADC), comprising:
- a pipelined stage, for receiving and converting a sampled and held direct-current voltage so as to output a first digital code and a residue voltage, and then converting the residue voltage so as to further output a second digital code, wherein the pipelined stage comprises:
- a switched capacitor circuit;
- and
- an operational amplifier, constituting a closed-loop with the switched capacitor circuit, and operating in an incomplete settling of a linear settling;
- and
- a combination unit, coupled to the pipelined stage, for receiving and combining the first and the second digital codes so as to output an original digital signal;
- and
- a digital background calibration unit, coupled to the combination unit and the pipelined stage, for receiving the original digital signal and the first and the second digital codes, and calibrating the original digital signal according to a reference digital signal and the first and the second digital codes, so as to output an accuracy digital signal.
5 more elements
Dependencies are inferred from the claim text.