Clock signal output circuit

Abstract

A clock signal output circuit includes a clock signal source which produces a clock signal, a buffer circuit which drives the clock signal while adjusting rise and fall times of the clock signal according to control signals, a rise-time frequency generator, responsive to the control signals, which produces a rise-time signal having a frequency corresponding to the rise time given by the buffer circuit, a fall-time frequency generator, responsive to the control signals, which produces a fall-time signal having a frequency corresponding to the fall time given by the buffer circuit, and a control signal generator which produces the control signals, based on the frequencies of the rise-time signal and fall-time signal.

Dependencies are inferred from the claim text.