Method of improving noise characteristics of an adpll and a relative adpll

A method of reducing noise of an all-digital phase locked loop (ADPLL) generating a feedback word representing a continuous-time oscillating signal, the ADPLL including a time-to-digital converter input with the continuous-time oscillating signal and a reference signal, the reference signal being a function of a reference clock signal, the time-to-digital converter (TDC) generating a digital word, the feedback word being based upon a function of the digital word, the method comprising:

• adding a pseudo-random sequence to at least one of the reference clock signal, the digital word, and the continuous-time oscillating signal;
• generating the reference signal by performing at least one of delaying the reference clock signal and delaying a replica of the continuous-time oscillating signal by a time value, the time value based upon a function of a level of the pseudo-random sequence;
• and
• generating the feedback word by adding the digital word to a dither signal, the dither signal being generated as an inverted and amplified replica of the pseudo-random sequence.

A device comprising:

• an all-digital phase locked loop generating a feedback word representing a continuous-time oscillating signal and comprising
• a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal, the reference signal being a function of a reference clock signal,
• said TDC being configured to generate a digital word, the feedback word being a function of the digital word,
• a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal,
• an inverting amplifier input with the first dither signal and configured to generate a second dither signal as an amplified replica of the first dither signal, and
• an adder configured to generate the feedback word as a sum of the digital word with the second dither signal.

An all-digital phase locked loop (ADPLL) generating a feedback word representing a continuous-time oscillating signal, the ADPLL comprising:

• a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal, the reference signal being a function of a reference clock signal;
• said TDC being configured to generate a digital word, the feedback word being a function of the digital word;
• a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal;
• and
• an inverting amplifier input with the first dither signal and configured to generate a second dither signal as an amplified replica of the first dither signal.