US 2010/0141313 A1 · DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING

Abstract

A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.

Claims30

Dependent claims

An apparatus comprising:

a digital phase-locked loop (DPLL) operative to perform two-point modulation via first and second modulation paths and to adaptively adjust delay of the first modulation path to match delay of the second modulation path.

Dependencies are inferred from the claim text.

Facts

Application

12/330,885Filed 9 Dec 2008

Published

10 Jun 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03C 3/0925
With frequency divider or counter in the loop: applying frequency modulation at the divider in the feedback loop
H03C 3/0933
With frequency divider or counter in the loop: using fractional frequency division in the feedback loop of the phase locked loop
H03C 3/0941
Using a phase locked loop: applying frequency modulation at more than one point in the loop
H03C 3/095
Using a phase locked loop: applying frequency modulation to the loop in front of the voltage controlled oscillator

Digital phase-locked loop with two-point modulation and adaptive delay matching

Life of this patent

Digital phase-locked loop with two-point modulation and adaptive delay matching

Life of this patent

Abstract

Claims30