Operating clock generation system and method for audio applications

An apparatus comprising:

• a clock signal multiplication circuit having:
• an oscillator that generates an oscillator signal;
• a counter circuit that is clocked by the oscillator signal and that receives a reference clock signal;
• a filter and estimator circuit that is coupled to the counter circuit;
• a delta-sigma modulator that is coupled to the filter and estimator circuit, wherein the delta-sigma modulator produces a plurality of integer representations of an estimate of the period of the reference clock signal multiplied by a ratio of the frequency of the reference clock signal to a predetermined frequency;
• a memory that is coupled to the delta-sigma modulator that stores the integer representations;
• and
• a divider that divides the oscillator signal by the integer representations;
• and
• a PLL having a reference input that is coupled to the divider, wherein the predetermined frequency is a lower threshold frequency for the operation of the PLL.

A method comprising:

• producing an estimate that is representative of a period of a first clock signal multiplied by a ratio of a predetermined frequency to a frequency of the first clock signal;
• producing a plurality of integer representations of the estimate with a sigma-delta modulator;
• storing the integer representations in a memory;
• dividing an oscillator clock signal by each integer representation from the memory to generate a pulse which lasts during a number of cycles of the oscillator clock signal equal to the value of that integer representation so as to generate the second clock signal;
• receiving the second clock signal at a reference clock input of a PLL, wherein the predetermined frequency is a lower threshold frequency for the operation of the PLL;
• and
• generating an output clock signal with the PLL, wherein the output clock signal is phase-locked with respect to the first clock signal.