Permutable switching network with enhanced multicasting signals routing for interconnection fabric

A method to manufacture an integrated circuit, comprising:

• fabricating a L-level permutable switching network (L-PSN),
• wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:
• wherein the (L+2) levels of conductors comprises:
• for i=[1:L], (I[i]/D[i])>1, D[i]>1, L≧1, at least one j where D[j]>2 for j selected from j=[1:L], each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors,
• an 0-th level of conductors of I[0] number of conductors,
• wherein (I[0]/Πi=[1:L]D[i])>1;
• an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,
• wherein D[L+1]>2 and (I[L+1]/D[L+1])=Πi=[1:L]D[i]
• wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1];
• selectively coupling the I[i−1] number of conductors of the (i−1)-th level of conductors to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1];
• for an j selected from j=[1:L] and DS[j]=(I[j−1]/I[j])×D[j], the I[j−1] number of conductors of the (j−1)-th level of conductors comprising (I[j−1]/DS[j]) groups of DS[j] number of conductors,
• selectively coupling each of the DS[j] number of conductors of the (I[j−1]/DS[j]) groups to one conductor in each of the D[j] sets of conductors of the j-th level of conductors through a respective DS[j] number of switches of the respective I[j−1] number of switches;
• physically connecting the Πi=[1:L]D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors to a corresponding number of pins of a corresponding module;
• and
• for T>1 and L>1, selectively coupling any DS[j+1] groups of DS[j] number of conductors of (T×DS[j+1]) groups of DS[j] number of conductors of the (j−1)-th level of conductors to DS[j+1] number of conductors in each of the D[j] sets of conductors of T groups of DS[j+1] number of conductors of the j-th level of conductors of D[j] sets of conductors through a respective (DS[j+1]×DS[j]×D[j]) number of switches,
• selectively coupling the DS[j+1] groups of DS[j] number of conductors to the conductors of at least two groups of DS[j+1] number of conductors of at least one of the D[j] sets of conductors of the T groups of DS[j+1] number of conductors through a respective (DS[j+1]×DS[j]) number of switches of the (DS[j+1]×DS[j]×D[j]) number of switches.

An article of manufacture comprising a machine readable storage medium that stores data representing an integrated circuit layout, comprising:

• a L-level permutable switching network (L-PSN);
• wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:
• wherein the (L+2) levels of conductors comprises:
• for i=[1:L], (I[i]/D[i])>1, D[i]>1, L≧1, at least one j where D[j]>2 for j selected from j=[1:L], each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors,
• an 0-th level of conductors of I[0] number of conductors,
• wherein (I[0]Πi=[1:L]D[i])>1;
• an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,
• wherein D[L+1]>2 and (I[L+1]/D[L+1])=Πi=[1:L]D[i];
• wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1];
• wherein the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1];
• for an j selected from j=[1:L] and DS[j]=(I[j−1]/I[j])×D[j], the I[j−1] number of conductors of the (j−1)-th level of conductors comprising (I[j−1]DS[j]) groups of DS[j] number of conductors,
• wherein each of the DS[j] number of conductors of the (I[j−1]/DS[j]) groups selectively couple to one conductor in each of the D[j] sets of conductors of the j-th level of conductors through a respective DS[j] number of switches of the respective I[j−1] number of switches;
• wherein the Πi=[1:L]D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module;
• and
• for T>1 and L>1, any DS[j+1] groups of DS[j] number of conductors of (T×DS[j+1]) groups of DS[j] number of conductors of the (j−1)-th level of conductors selectively couple to DS[j+1] number of conductors in each of the D[j] sets of conductors of T groups of DS[j+1] number of conductors of the j-th level of conductors of D[j] sets of conductors through a respective (DS[j+1]×DS[j]×D[j]) number of switches,
• wherein the DS[j+1] groups of DS[j] number of conductors selectively couple to the conductors of at least two groups of DS[j+1] number of conductors of at least one of the D[j] sets of conductors of the T groups of DS[j+1] number of conductors through a respective (DS[j+1]×DS[j]) number of switches of the (DS[j+1]×DS[j]×D[j]) number of switches.