Stacked chip, micro-layered lead frame semiconductor package

A semiconductor package, comprising:

• a land pad array comprising a middle portion and an outer portion;
• a first die containing an integrated circuit device resting on part of the middle portion of the land pad array;
• a second die containing an integrated circuit device resting on the part of the middle portion of the land pad array;
• a third die disposed over the first and second dies and resting on routing leads that are connected to the outer portion of the land pad array;
• and
• a molding material.

An electronic device containing a semiconductor package, the package comprising:

• a land pad array comprising a middle portion and an outer portion;
• a first die containing an integrated circuit device resting on the middle portion of the land pad array;
• a second die containing an integrated circuit device disposed over the first die and resting on first routing leads that are connected to part of the outer portion of the land pad array;
• a third die containing an integrated circuit device disposed on the backside of the second die and resting on second routing leads that are connected to part of the outer portion of the land pad array;
• and
• a molding material.

An electronic device containing a semiconductor package, the package comprising:

• a land pad array comprising a middle portion and an outer portion;
• a first die containing an integrated circuit device resting on part of the middle portion of the land pad array;
• a second die containing an integrated circuit device resting on the part of the middle portion of the land pad array;
• a third die disposed over the first and second dies and resting on routing leads that are connected to the outer portion of the land pad array;
• and
• a molding material.

A method for making semiconductor package, comprising:

• providing a lead frame containing an array of vias;
• attaching a first die containing an integrated circuit device to a die attach pad of the leadframe;
• providing a first molding material around the array of vias and the first die so that the upper surfaces of the vias are exposed;
• providing first routing leads from the vias to the backside of the first die;
• attaching a second die containing an integrated circuit device to the first routing leads;
• providing a second molding material around the first via extensions and the second die so that the upper surfaces of the via extensions are exposed;
• providing second routing leads from the vias to the backside of the second die;
• attaching a third die containing an integrated circuit device to the second routing leads;
• providing a third molding material to encapsulate the second routing leads and third die;
• and
• etching the lead frame to form a land pad array.

A method for making semiconductor package, comprising:

• providing a lead frame with an array of vias and a die attach pad;
• attaching a first die containing an integrated circuit device to the die attach pad;
• attaching a second die containing an integrated circuit device to the die attach pad;
• providing a first molding material around the array of vias, the first die, and the second fie so that the upper surfaces of the vias are exposed;
• providing routing leads from the vias to the backside of the first die and the second die;
• attaching a third die containing an integrated circuit device to the routing leads;
• providing a second molding material around the second routing leads and third die;
• and
• etching the lead frame to form a land pad array.