Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby

A semiconductor device having a multiple channel transistor comprising:

• a semiconductor substrate having a first and second isolation regions, the first and second isolation regions defining an active region;
• a first semiconductor pillar having sidewalls in the active region, a portion of the sidewalls of the first semiconductor pillar in contact with the first isolation region;
• second and third semiconductor pillars in the active regions, the second and third semiconductor pillars being spaced apart from the first semiconductor pillar respectively;
• a first recessed region between the first and second semiconductor pillars;
• a second recessed region between the second and third semiconductor pillars;
• a first buffer insulating layer pattern in the first recessed region;
• a second buffer insulating layer pattern in the second recessed region;
• a gate dielectric layer on the surface of the first semiconductor pillars, the second semiconductor pillars, the third semiconductor pillars, the first buffer insulating layer pattern, and the second buffer insulating layer pattern;
• and
• a gate electrode on the gate dielectric layer.