Double Polysilicon Process for Non-Volatile Memory

A process flow for creating a non-volatile memory cell, the process flow comprising the steps of:

• forming a doped well in a semiconducting portion of a substrate,
• forming a gate dielectric layer on top of the substrate,
• depositing a first polysilicon layer on top of the gate dielectric layer,
• patterning and etching the first polysilicon layer,
• forming lightly-doped spurce/drain regions into the well,
• depositing a dielectric layer on top of the first polysilicon layer,
• depositing a second polysilicon layer on top of the dielectric layer,
• forming a masking layer on the second polysilicon layer,
• etching both the second polysilicon layer and the dielectric layer using the masking layer,
• forming sidewall spacers adjacent the first polysilicon layer, the dielectric layer, and the second polysilicon layer, and
• implanting source/drain regions into the well.

A process flow for creating a non-volatile memory cell, the process flow comprising the steps of:

• forming a doped well in a semiconducting portion of a substrate,
• forming a gate dielectric layer on top of the substrate,
• depositing a first polysilicon layer on top of the gate dielectric layer,
• patterning and etching the first polysilicon layer,
• performing a blanket implant to form lightly-doped source/drain regions in the non-volatile memory cell,
• depositing a dielectric layer on top of the first polysilicon layer,
• depositing a second polysilicon layer on top of the dielectric layer,
• forming a masking layer on the second polysilicon layer,
• etching both the second polysilicon layer and the dielectric layer,
• patterning and etching the first polysilicon layer in logic areas,
• forming lightly-doped source/drain regions into the well,
• forming sidewall spacers adjacent the first polysilicon layer, the dielectric layer, and the second polysilicon layer, and
• implanting source/drain regions into the well.

A process flow for creating a non-volatile memory cell, the process flow comprising the steps of:

• forming a doped well in a semiconducting portion of a substrate,
• forming a gate dielectric layer on top of the substrate,
• depositing a first polysilicon layer on top of the gate dielectric layer,
• selectively implanting a dopant species into the first polysilicon layer,
• forming a floating gate mask,
• selectively etching the first polysilicon layer using the floating gate mask,
• depositing a dielectric layer on top of the first polysilicon layer,
• depositing a second polysilicon layer on top of the dielectric layer,
• forming a masking layer on the second polysilicon layer,
• selectively etching the second polysilicon layer, the dielectric layer using the masking layer, and the first polysilicon layer,
• forming an array masking layer on top of the second polysilicon layer,
• removing the second polysilicon layer and the dielectric layer from logic areas,
• patterning and etching the first polysilicon layer,
• forming lightly-doped source/drain regions into the well,
• forming sidewall spacers adjacent the first polysilicon layer, the dielectric layer, and the second polysilicon layer, and
• implanting source/drain regions into the well.

A process flow for creating a non-volatile memory cell, the process flow comprising the steps of:

• forming a doped well in a semiconducting portion of a substrate,
• forming a gate dielectric layer on top of the substrate,
• depositing a first polysilicon layer on top of the gate dielectric layer,
• selectively implanting a dopant species into the first polysilicon layer,
• patterning and etching the first polysilicon layer,
• depositing a dielectric layer on top of the first polysilicon layer,
• depositing a second polysilicon layer on top of the dielectric layer,
• forming a masking layer on the second polysilicon layer,
• selectively etching the second polysilicon layer, the dielectric layer using the masking layer, and the first polysilicon layer,
• forming an array masking layer on top of the second polysilicon layer,
• removing the second polysilicon layer and the dielectric layer from logic areas,
• forming lightly-doped source/drain regions into the well,
• forming sidewall spacers adjacent the first polysilicon layer, the dielectric layer, and the second polysilicon layer, and
• implanting source/drain regions into the well.

A non-volatile memory cell, comprising:

• a semiconducting substrate,
• a source portion formed in the semiconducting substrate,
• a drain portion formed in the semiconducting substrate,
• an active area formed in the semiconducting substrate and extending in a strip in x-coordinate directions between the source portion and the drain portion, and
• a first polysilicon gate layer formed above the semiconducting substrate and crossing the active area in y-coordinate directions between the source portion and the drain portion, the gate extending outside the strip of the active area in both of the y-coordinate directions.