Logic verification apparatus

Abstract

To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a description of the logic function described in a hardware description language. A second symbol replacing part replaces an indeterminate value generated in the simulation by the simulation part with a symbol. The simulation part generates a symbol expression and propagates it to an element at a later stage when the symbol replaced by the second symbol replacing part reaches an element being processed. Therefore, unintentional erasing of the indeterminate value generated during the simulation can be prevented.

Dependencies are inferred from the claim text.