Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

An apparatus for maintaining inclusion of a processor pipeline, the apparatus comprising:

• a first micro-op cache line having a first way storage field to record an instruction-cache way storing a first instruction corresponding to one or more micro-ops, generated by decoding the instruction, said one or more micro-ops also to be stored in the first micro-op cache line;
• an instruction-cache in-use indication associated with the first instruction, said instruction-cache in-use indication to be updated, responsive to a micro-op cache hit at the first micro-op cache line, and locatable at least in part through use of the instruction-cache way recorded for the first micro-op cache line;
• a micro-op queue to enqueue a victim-cache deallocation micro-op after a micro-op cache miss synchronization initiated responsive to an eviction of the first instruction from the instruction-cache into a victim-cache;
• and
• inclusion logic to locate and to evict the first micro-op cache line corresponding to the recorded instruction-cache way, responsive to the eviction of the first instruction from the instruction-cache.

An article of manufacture including a machine readable medium, said machine readable medium storing state and/or executable data, which when accessed by one or more machines causes said one or more machines to:

• record, for a first micro-op cache line, a first instruction-cache way storing a first instruction corresponding to one or more micro-ops, generated by decoding the first instruction, and to be stored in the first micro-op cache line;
• update, responsive to a micro-op cache hit at the first micro-op cache line, an instruction-cache in-use indication associated with the first instruction, said instruction-cache in-use indication associated with the first instruction being located at least in part through use of the first instruction-cache way recorded for the first micro-op cache line;
• evict the first micro-op cache line corresponding to the recorded first instruction-cache way, and initiate a micro-op cache miss synchronization responsive to an eviction of the first instruction from the instruction-cache;
• and
• enqueue a victim-cache deallocation micro-op following the micro-op cache miss synchronization.