Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure

A method of forming a gate electrode structure of a transistor, the method comprising:

• forming a protection liner on sidewalls of a gate stack, said gate stack being formed above a semiconductor layer and comprising a high-k dielectric gate insulation layer, a metal-containing electrode material formed on said high-k dielectric gate insulation layer and a cap layer;
• forming a mask material above said semiconductor layer so as to cover said protection liner at least at a bottom of said gate stack;
• and
• removing said cap layer in the presence of said mask material.

A method, comprising:

• forming a mask material laterally adjacent to a first gate stack of a first transistor and a second gate stack of a second transistor, said first and second gate stacks being formed on a semiconductor layer and comprising a high-k dielectric material;
• removing at least one of a first cap layer provided in said first gate stack and a second cap layer provided in said second gate stack in the presence of said mask material;
• and
• forming first drain and source regions of said first transistor and second drain and source regions of said second transistor after removing said at least one of said first and second cap layers.