Operation method of semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsWon-joo Kim, Sang-moo Choi, Tae-hee Lee
Life of this patent
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Abstract
Provided is a method of operating a semiconductor device, in which timing for switching each of a drain voltage pulse signal and a gate voltage pulse signal from a first state to a second state is controlled in an erase mode and a write mode.
Claims22
A method of operating a semiconductor device including a plurality of memory cells, each memory cell including a drain region, a source region, a floating body region, and a gate electrode, the method comprising:
- switching a gate voltage pulse signal supplied to the gate electrode from a gate enable voltage to a gate standby voltage after a drain voltage pulse signal supplied to the drain region is switched from a drain enable voltage to a drain standby voltage, to change a data state of at least one of memory cells to a first state if in an erase mode;
- and
- switching the drain voltage pulse signal from the drain enable voltage to the drain standby voltage after the gate voltage pulse signal is switched from the gate enable voltage to the gate standby voltage, to change the data state of at least one of memory cells to a second state if in a write mode;
- wherein
- the drain standby voltage is higher than the drain enable voltage, and
- the gate enable voltage is higher than the gate standby voltage.
A method of erasing data from a plurality of memory cells, each memory cell including a drain region, a source region, a floating body region, and a gate electrode, the method comprising:
- if in an erase mode
- switching a drain voltage pulse signal supplied to the drain region;
- and
- one of switching the gate voltage pulse signal from a gate enable voltage to a gate standby voltage after the drain voltage pulse signal from a drain enable voltage to a drain standby voltage, and switching the gate voltage pulse signal from the gate enable voltage to the gate standby voltage at the same time that the drain voltage pulse signal is switched from the drain enable voltage to the drain standby voltage, wherein the drain standby voltage is higher than the drain enable voltage, and the gate enable voltage is higher than the gate standby voltage.
A method of writing data to a plurality of memory cells, each memory cell including a drain region, a source region, a floating body region, and a gate electrode, the method of writing data comprising:
- switching a drain voltage pulse signal supplied to the drain region from a standby voltage to an enable voltage before, after or at the same time that a gate voltage pulse signal supplied to the gate electrode is switched from a standby voltage to an enable voltage;
- and
- switching the drain voltage pulse signal from the enable voltage to the standby voltage after the gate voltage pulse signal is switched from the enable voltage to the standby voltage, or the gate voltage pulse signal is switched from the enable voltage to the standby voltage at the same time that the drain voltage pulse signal is switched from the enable voltage to the standby voltage, wherein the standby voltage of the drain voltage pulse signal is higher than the enable voltage of the drain voltage pulse signal, and an enable voltage of the gate voltage pulse signal is higher than a standby voltage of the gate voltage pulse signal.
Dependencies are inferred from the claim text.