Antifuse Circuit Having Protection Circuit

A semiconductor device comprising:

• an antifuse circuit;
• and
• a plurality of pins or balls for connecting the semiconductor device to an external circuit that contains an external power supply for supplying an antifuse program voltage, wherein a non-connected (NC) pin or ball of the plurality of pins or balls is configured to deliver the antifuse program voltage from the external power supply to the antifuse circuit,
• the antifuse circuit comprising:
• a protection circuit including a first protection unit connected between a first pad and a common node, and configured to apply a program voltage, received from the first pad, to the common node when the program voltage is higher than a boost voltage and the first protection unit is configured to prevent application of the program voltage to the common node when the program voltage is lower than the boost voltage;
• and
• at least one antifuse unit each including an antifuse, and configured to program the antifuse in response to a selection signal and a program mode signal in a program mode and output an output signal according to a program state of the antifuse in a normal mode.

A semiconductor device comprising:

• an antifuse circuit;
• and
• a plurality of pins or balls for connecting the semiconductor device to an external circuit that contains an external power supply for supplying an antifuse program voltage, wherein a non-connected (NC) pin or ball of the plurality of pins or balls is configured to deliver the antifuse program voltage from the external power supply to the antifuse circuit,
• the antifuse circuit comprising:
• a protection circuit including a first protection unit connected between a first pad and a common node, and configured to apply a program voltage, received from the first pad, to the common node when the program voltage is higher than a boost voltage and the first protection unit is configured to prevent application of the program voltage to the common node when the program voltage is lower than the boost voltage;
• and
• at least one antifuse unit each including an antifuse, and configured to program the antifuse in response to a selection signal and a program mode signal in a program mode and output an output signal according to a program state of the antifuse in a normal mode, wherein the first protection unit comprises:
• a PMOS transistor connected between the first pad and the common node, comprising a gate to which the boost voltage is applied, a p-type substrate, an n-type well disposed in a predetermined region of the p-type substrate, a p-type source and a p-type drain disposed in a first and second predetermined region of the n-type well, respectively, the p-type source and the p-type drain being spaced apart from each other, an n-type well electrode disposed in a third predetermined region of the n-type well and functioning as a body of the PMOS transistor, the n-type well electrode being spaced apart from the p-type source and p-type drain, and connected to a cathode of the diode, the n-type well electrode being used to apply a bias voltage to the n-type well, a dielectric material disposed on the n-type well between the p-type source and the p-type drain, and a gate disposed on the dielectric material, and configured to receive the boost voltage;
• and
• a diode connected between a body of the PMOS transistor and a power supply voltage that is lower than the boost voltage, wherein the n-type well electrode applys the external power supply voltage as a bias voltage through a diode to the body of the PMOS transistor.