Phase Detector Circuit for Automatically Detecting 270 and 540 Degree Phase Shifts

A phase detector for use in a circuit comprising:

• a first series of delay gates receiving a system clock signal;
• a second series of delay gates receiving a substantially 270 degree phase shifted clock signal;
• a third series of delay gates receiving a substantially 540 degree phase shifted clock signal;
• a first flip-flop circuit receiving the system clock signal and a second order delayed signal of the substantially 270 degree phase shifted clock signal;
• a second flip-flop circuit receiving the system clock and a second order delayed signal of the substantially 540 degree phase shifted clock signal;
• and
• a NOR gate receiving outputs from the first flip-flop circuit and second flip-flop circuit and generating an up control signal and a down control signal.

A method comprising:

• providing a system clock signal to a delay line;
• generating a substantially 270 degree phase shifted signal and a substantially 540 degree phase shifted signal in the delay line;
• providing the system clock signal and the substantially 270 degree phase shifted signal to a phase detector stage;
• generating an up control signal when the phase difference between the system clock signal and the substantially 540 degree phase shifted signal is between substantially 540 to substantially 720 degrees;
• and
• generating a down control signal when the phase difference between the system clock signal and the substantially 540 degree phase shifted signal is between substantially 0 to substantially 540 degrees.

A computer readable media storing computer readable instructions adapted to enable manufacture of a circuit comprising:

• a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal;
• a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal;
• a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto;
• and
• a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.