Apparatus and method for reducing pitch in an integrated circuit

An electronic chip package comprising:

• an electronic chip having a first contact pad and a second contact pad positioned adjacent the first contact pad;
• and
• a build-up structure positioned on the electronic chip and over the first and second contact pads, the build-up structure comprising:
• a first and a second dielectric layer having a dielectric boundary therebetween;
• a first cover pad having a first cover pad aperture therethrough and positioned along the dielectric boundary;
• a second cover pad having a second cover pad aperture therethrough and positioned along the dielectric boundary;
• and
• wherein the build-up structure has a first and a second multi-layer via therethrough;
• the first multi-layer via extending through the second dielectric layer, the first cover pad aperture, and the first dielectric layer to the first contact pad;
• and the second multi-layer via extending through the second dielectric layer, the second cover pad aperture, and the first dielectric layer to the second contact pad.

A method for minimizing contact pad pitch of an electronic chip package comprising:

• providing an electronic chip having a first and a second contact pad thereon, wherein the first and second contact pads are free of an intervening contact pad therebetween;
• forming a build-up structure on the electronic chip, the build-up structure having a first dielectric layer coupled to a second dielectric layer, wherein forming the build-up structure comprises:
• providing a first and a second cover pad to a one of a top surface of the first dielectric layer and a bottom surface to the second dielectric layer;
• forming a first multi-layered via through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad;
• and
• forming a second multi-layered via through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.