US 2010/0133702 A1Published application

Method for eliminating loading effect using a via plug

AssigneeSemiconductor Manufacturing International (Shanghai) Corporation

InventorsWu XiangHui, Ching-Tien Ma, Man Hua Shen, Chi Yu Shan

Life of this patent

Estimating the term…

Loading patent…

Abstract

Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

Claims23

Dependent claims

A method of processing an integrated circuit wherein a loading effect is reduced, the method comprising:

providing a substrate, the substrate being characterized by a first thickness;
forming an inter metal dielectric layer overlaying the substrate, the inter metal dielectric layer being characterized by a second thickness;
forming a first photoresist layer overlaying the inter metal dielectric layer, the first photoresist layer being associated with a first pattern;
forming a first opening positioned at least partially inside the inter metal dielectric layer, the first opening being characterized by a first depth;
removing the first photoresist layer;
forming a via plug, the via plug being positioned in side the first opening, the via plug being characterized by a first plurality of dimensions, the first plurality of dimensions comprising a first height and a first width, the first height being less than or equal to the first depth;
forming a first filling layer overlaying the first opening;
forming a second photoresist layer overlaying the first filling layer, the second photoresist layer being associated with a second pattern;
forming a second opening positioned at least partially inside the inter metal dielectric layer, the second opening being characterized by second plurality of dimensions, the second plurality of dimensions comprising a second depth and a second width, the second depth being less than the first depth, and
removing the via plug and the second photoresist layer.

7 more elements

Dependencies are inferred from the claim text.