Semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a first p-type MOS transistor having first diffused regions extending parallel with a first direction, and having a first gate electrode extending parallel with the first direction;
• a first n-type MOS transistor having second diffused regions extending parallel with the first direction, and having a second gate electrode extending parallel with the first direction, with STI disposed for device isolation between the first n-type MOS transistor and the first p-type MOS transistor substantially in parallel with a second direction, the second direction being perpendicular to the first direction;
• second p-type MOS transistors having third gate electrodes disposed so as to be adjacent to the first diffused regions of the first p-type MOS transistor, the third gate electrodes being connected to power supply wiring;
• and
• second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor, the fourth gate electrodes being connected to ground wiring,
• wherein the second p-type MOS transistor has a gate length greater than a gate length of the first p-type MOS transistor, and
• the second n-type MOS transistor has a gate length greater than a gate length of the first n-type MOS transistor.

A semiconductor integrated circuit comprising:

• a first p-type MOS transistor having first diffused regions extending parallel with a first direction, and having a first gate electrode extending parallel with the first direction;
• a first n-type MOS transistor having second diffused regions extending parallel with the first direction, and having a second gate electrode extending parallel with the first direction, with STI disposed for device isolation between the first n-type MOS transistor and the first p-type MOS transistor substantially in parallel with a second direction, the second direction being perpendicular to the first direction;
• second p-type MOS transistors having third gate electrodes disposed so as to be adjacent to the first diffused regions of the first p-type MOS transistor, the third gate electrodes being connected to power supply wiring;
• and
• second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor, the fourth gate electrodes being connected to ground wiring,
• wherein the third gate electrodes are connected to the power supply wiring formed on a wiring layer disposed above a layer in which the third gate electrodes are formed, and
• the fourth gate electrodes are connected to the ground wiring formed on a wiring layer disposed above a layer in which the fourth gate electrodes are formed.