Method and apparatus for designing an integrated circuit
AssigneeFreescale Semiconductor, Inc.
InventorsLionel J. Riviere-Cazeaux, Ashish Rajput
Life of this patent
Estimating the term…
Abstract
Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects.
Claims22
A method of designing an integrated circuit, IC, layout comprising:
- identifying one or more defects in a feature within the IC layout during a design stage of the IC layout;
- determining if an identified defect is improvable
- calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects;
- comparing the improvability metric with a predetermined threshold;
- and
- reworking the IC layout when the improvability metric exceeds the predetermined threshold.
A method of analysing an IC layout comprising:
- identifying defects in the IC layout during a design stage of the IC layout;
- categorising each identified defect according to severity of the defect;
- summing the defects falling within each category;
- applying a predetermined weighting factor to the sum of defects within each category;
- and
- calculating a manufacturability metric of the IC layout based on the weighted sum of the defects.
A computer readable medium comprising program instructions that, when executed on a computer cause the computer to perform operations comprising:
- identifying one or more defects in a feature within the IC layout during a design stage of the IC layout;
- determining if an identified defect is improvable;
- calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects;
- comparing the improvability metric with a predetermined threshold;
- and
- reworking the IC layout when the improvability metric exceeds the predetermined threshold.
(canceled)
Apparatus for designing an integrated circuit, IC, comprising:
- means for identifying one or more defects in a feature within an IC layout for use within a design stage of the IC;
- means for determining if an identified defect is improvable;
- and
- means for calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects;
- means for comparing the improvability metric with a predetermined threshold;
- and
- means for reworking the IC layout when the improvability metric exceeds the predetermined threshold.
(canceled)
Dependencies are inferred from the claim text.