Apparatus and method for testing setup/hold time
AssigneeHynix Semiconductor Inc.
InventorJeong Hun Lee
Life of this patent
Estimating the term…
Abstract
An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.
Claims22
An apparatus for testing setup/hold time, comprising:
- a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals;
- and
- an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals in response to a test mode signal by using the input data.
A method for testing setup/hold time, comprising:
- calibrating a level of output data of an off-chip driver according to first input data when a test mode is in a disabled state;
- and
- calibrating setup/hold time of a selected data input unit among a plurality of data input units according to second input data when a test mode is in an enabled state.
A method for testing setup/hold time, comprising:
- decoding data input to input terminals of an off-chip driver calibration unit through a first signal path to output a first decoded signal when a test mode signal is in a disabled state;
- and
- calibrating a level of output data of an off-chip driver according to the first decoded signal,
- wherein the off-chip driver calibration unit decodes data input to the input terminal through a second signal path to output a second decoded signal when the test mode signal is in an enabled state, and calibrates setup/hold time of a data input unit selected among the plurality of data input units according to the second decoded signal.
An apparatus for testing setup/hold time, comprising:
- an input buffer configured to receive input data;
- a setup/hold calibration unit configured to calibrate setup/hold time of the input data by delaying an output signal of the input buffer by as much as a delay time corresponding to the setup/hold calibration signals enabled according to the selection signals;
- a pre-fetch circuit unit configured to pre-fetch an output signal of the setup/hold calibration unit to output pre-fetched data;
- a first latch circuit unit configured to latch the pre-fetched data to output latched data;
- and
- a plurality of decoders, each configured to decode the latched data to output one of off-chip driver calibration signals, the selection signals, and the setup/hold calibration signals.
A semiconductor memory apparatus, comprising:
- a plurality of data input units calibrating setup/hold time of input data in response to selection signals and setup/hold calibration signals;
- and
- an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units,
- wherein memory data is written into memory regions according to the setup/hold time of the input data.
Dependencies are inferred from the claim text.