Multi-port dram architecture

A memory device, comprising:

• at least one memory array comprising a plurality of predefined sections of memory;
• a command receiver circuit configured to receive command signals from at least one processing unit, wherein the command signals are received from the at least one processing unit via a command/address (CA) port of the memory device;
• a command decoder circuit configured to receive commands from the command receiver circuit and generate one or more control signals for accessing the memory array;
• an address receiver circuit configured to receive address signals from the at least one processing unit via the CA port;
• and
• a data input/output (IO) circuit configured to exchange data signals with the at least one processing unit via a plurality of data ports, each data port being associated with a different predefined section of the memory array and being configured to transfer data to and from the respective predefined section.

A system, comprising:

• at least one processing unit;
• and
• a memory device comprising:
• at least one memory array comprising a plurality of predefined sections of memory;
• at least one command/address (CA) port configured to receive command and address signals from at least one processing unit for accessing the at least one memory array;
• and
• a plurality of data ports, each data port being associated with a different predefined section of the memory array and being configured to transfer data to and from the section of the memory array associated therewith.

A memory device, comprising:

• at least one memory array comprising a plurality of predefined sections of memory;
• a plurality of command/address (CA) ports, each CA port being configured to receive command and address signals from a respective processing unit of a plurality of processing units for accessing the at least one memory array;
• and
• a plurality of data ports, each data port being associated with a different one of the plurality of CA ports, wherein each data port is associated with a different predefined section of the memory array and is configured to transfer data to and from the section of the memory array associated therewith.