Transistor Forming Methods
AssigneeMicron Technology, Inc.
InventorJasper Gibbons
Life of this patent
Estimating the term…
Abstract
A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and forming a gate line extending through the line openings, over opposing sidewalls, and over a top of the fin. Source/drain regions are in the fin. Another method includes forming an interlayer dielectric over areas of the fin intended for source/drain regions, forming contact openings through the interlayer dielectric, and forming a source/drain plug in contact with an exposed portion of the spacer and in electrical connection with the top, one of opposing endwalls, and both of the opposing sidewalls of the fin.
Claims21
1-27. (canceled)
A transistor forming method comprising:
- providing an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate, the island having a fin of semiconductor material and the fin having a top, opposing sidewalls, and opposing endwalls and a portion of the island extending from the fin to an edge of the island;
- forming a dielectric spacer around the fin and over the portion of the island between the fin and the edge of the island, over the opposing sidewalls, and over the opposing endwalls, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness;
- forming line openings through the spacer and exposing through the line openings some of the semiconductor material between the fin and the edge of the island and some of the semiconductor material of the opposing sidewalls of the fin;
- forming a gate line on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin;
- and
- in operational association with the gate line, forming source/drain regions in the fin.
A transistor forming method comprising:
- providing an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate, the island having a fin of semiconductor material and the fin having a top, opposing sidewalls, and opposing endwalls;
- forming a dielectric spacer around the fin and over the opposing sidewalls and the opposing endwalls, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness;
- forming a gate line on and in contact with the semiconductor material exposed above the spacer, the gate line extending over the opposing sidewalls and over the top of the fin;
- forming an interlayer dielectric over areas of the fin intended for source/drain regions and over the spacer;
- and
- forming contact openings through the interlayer dielectric and exposing the areas intended for source/drain regions and at least a portion of the spacer proximate the areas, the spacer providing an etch stop for the forming of the contact openings;
- in operational association with the gate line, forming the source/drain regions in the fin;
- and
- forming source/drain plugs through the contact openings in contact with the exposed portions of the spacer and in electrical connection with at least the top and both of the opposing sidewalls of the fin of the source/drain regions.
Dependencies are inferred from the claim text.