US 2010/0073990 A1 · Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays

Abstract

Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

Claims36

Dependent claims

An integrated circuit, comprising:

a non-volatile two-terminal cross-point memory array including a plurality of two-terminal memory cells, each two-terminal memory cell operative to store data as a plurality of conductivity profiles;
and
a substrate including active circuitry in electrical communication with the non-volatile two-terminal cross-point memory array, the non-volatile two-terminal cross-point memory array is fabricated over the substrate and is in contact with the substrate, the active circuitry including
a memory access circuit configured to select at least one of the plurality of two-terminal memory cells for a read operation,
a sensing circuit configured to sense a data signal from selected two-terminal memory cells, the data signal indicative of stored data in selected two-terminal memory cells, and
a margin manager circuit configured to manage a read margin for selected two-terminal memory cells substantially during the read operation and operative to determine if a value of the stored data in selected two-terminal memory cells is within a specified level of the read margin.

3 more elements

Dependencies are inferred from the claim text.

Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays

Life of this patent

Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays

Life of this patent

Abstract

Claims36