Pixel circuit and display device

A pixel circuit, disposed so as to correspond to each intersection between a scanning line and a data line, which includes a current-driven electrooptic element, the pixel circuit comprising:

• first to third power supply wires;
• a control wire;
• a driving transistor;
• first and second switching transistors;
• and
• first and second capacitors,
• the electrooptic element being connected between the first power supply wire and a second conducting terminal of the driving transistor, a first conducting terminal of the driving transistor being connected to the second power supply wire, the second conducting terminal of the driving transistor being connected through the first switching transistor to a control terminal of the driving transistor, a control terminal of the first switching transistor being connected to the control wire, the control terminal of the driving transistor being connected through the first capacitor to a node, the node being connected through the second switching transistor to the data line, a control terminal of the second switching transistor being connected to the scanning line, the node being connected through the second capacitor to the third power supply wire.

A pixel circuit, disposed so as to correspond to each intersection between a scanning line and a data line, which includes a current-driven electrooptic element, the pixel circuit comprising:

• first to third power supply wires;
• a control wire;
• a driving transistor;
• first and second switching transistors;
• and
• first and second capacitors,
• the electrooptic element being connected between the first power supply wire and a second conducting terminal of the driving transistor, a first conducting terminal of the driving transistor being connected to the second power supply wire, the second conducting terminal of the driving transistor being connected through the first switching transistor to a control terminal of the driving transistor, a control terminal of the first switching transistor being connected to the control wire, the control terminal of the driving transistor being connected to a first node, the first node being connected through the first capacitor to a second node, the second node being connected through the second switching transistor to the data line, a control terminal of the second switching transistor being connected to the scanning line, the first node being connected through the second capacitor to the third power supply wire.