Inductor with a decreased surface area and an improved ability to conduct strong currents
AssigneeSTMicroelectronics S.r.l.
InventorFrederic Gianesello
Life of this patent
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Abstract
An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.
Claims9
An inductor formed in a stacking of insulating layers, the inductor comprising first and second access terminals, at least first and second interlaced loops on a first level (N1), and at least third and fourth interlaced loops on a second level (N2) distinct from the first level, the third loop being, as seen along the stacking direction, symmetrical with the first loop with respect to a plane (P′) and the fourth loop being, as seen along the stacking direction, symmetrical with the second loop with respect to said plane, internal ends of the first and second loops being connected to internal ends of the third and fourth loops, external ends of the first and third loops being connected to the first and second access terminals, and the external ends of the second and fourth loops being interconnected.
Dependencies are inferred from the claim text.