Stacking Package Structure with Chip Embedded Inside and Die Having Through Silicon Via and Method of the same
AssigneeKing Dragon International Inc.
InventorWen-Kun YANG
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Abstract
The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.
Claims19
A semiconductor device package structure, comprising:
- a first die with a through silicon via (TSV) open from back side of said first die to expose bonding pads;
- a build up layer coupled between said bonding pads to terminal metal pads by said through silicon via (TSV);
- a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of said substrate respectively;
- and
- a conductive through hole structure coupled between said terminal metal pads to said top circuit wiring and said bottom circuit wiring.
A method of forming a semiconductor die assembly, comprising:
- bonding a panel substrate facing to the backside of a silicon wafer;
- curing an adhesion dielectric layer that is formed on said panel substrate;
- sputtering a seed metal layer from the back side of said panel substrate;
- coating a photo resist from the back side of said panel substrate and opening a through hole area
- filling metal material into said through hole area to inter-connecting bonding pads of a die to final terminal pads of said panel substrate;
- and
- stripping said photo resist and etching said seed metal layer.
Dependencies are inferred from the claim text.