Circuit Arrangement Comprising a Memory Cell Field and Method for Operation Thereof
Assigneeaustriamicrosystems AG
InventorsPeter Bösmüller, Johannes Fellner
Life of this patent
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Abstract
A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).
Claims12
A circuit arrangement comprising a memory cell array with at least one memory circuit wherein the at least one memory circuit comprises:
- a non-volatile memory cell which is inserted in a first current path between a supply voltage terminal and a reference potential terminal and comprises a non-volatile memory element;
- a volatile memory cell which is inserted in a second current path between the supply voltage terminal and the reference potential terminal and comprises a first inverter, a second inverter in feed-back arrangement with the first inverter, and an address transistor inserted between an input of the first inverter and a bit line, the volatile memory cell being coupled to the non-volatile memory cell for reading and programming the non-volatile memory element;
- and
- a reading transistor coupling the non-volatile memory cell to a measuring line;
- wherein the circuit arrangement further comprises a comparator coupled between the non-volatile memory cell and the volatile memory cell so that a comparator input of the comparator is connected to the measuring line and a comparator output of the comparator is connected to the bit line, the comparator holding several threshold values and being designed for a selective comparison of a measuring signal of the measuring line with one of the several threshold values.
(canceled)
(canceled)
A method for operating a circuit arrangement comprising a memory cell array, including transferring an item of information of a non-volatile memory cell to a volatile memory cell in a reading step, with the non-volatile memory cell and the volatile memory cell each being comprised of a memory cell array, wherein the reading step comprises:
- providing a measuring signal depending on a parameter of the non-volatile memory cell;
- providing a bit signal by a comparator depending on a selective comparison of the measuring signal with one of several threshold values of the comparator;
- and
- providing the bit signal to the volatile memory cell.
Dependencies are inferred from the claim text.