Graphics-Processing Architecture Based on Approximate Rendering

Abstract

A graphics processing circuit for rendering three-dimensional graphics data is disclosed. The circuit includes pipelined graphics processing stages, wherein each of two or more of the stages is configured to process at least one of graphics primitives, vertices, tiles, and pixels, according to a stage-specific error budget. Depending on its error budget, each of these stages may select a high- or low-precision calculation, select between lossless and lossy compression, adjust the compression ratio of a variable lossy compression algorithm, or some combination of these approaches. The circuit further comprises a global error-control unit configured to determine error budgets for each of the two or more stages, based on at least one of error data received from the two or more stages, predetermined scene complexity data, and user-defined error settings, and to assign the error budgets to the graphics processing stages. Corresponding methods for processing graphics data are also disclosed.

Dependencies are inferred from the claim text.