Adiabatic cmos design
AssigneeKoninklijke Philips Electronics N.V.
InventorMart Coenen
Life of this patent
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Abstract
An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and a second transistor (52) is provided between one of the modules (10) and the second reference line (Vss) and capacitors (C25, C26) are provided in parallel with the transistors (52, 54) such that they are driven as current sources (I1, 12). As a result power dissipation and leakage current is reduced.
Claims11
A CMOS module connected between a first reference and a second reference line, a first transistor being present between said module and said first reference line and a second transistor being present between said module and said second reference line, wherein first capacitive means is provided in parallel with said first transistor and second capacitive means is provided in parallel with said second transistor such that, in use, said first and second transistors operate as first and second respective current sources.
A method of fabricating a CMOS module, the method comprising providing a CMOS circuit on a substrate, connecting said CMOS circuit between a first reference line and a second reference line via respective transistors being provided in series with said first and second reference lines, and providing first capacitive means in parallel with said first transistor and second capacitive means in parallel with said second transistor, such that, in use, said first and second transistors operate as first and second respective current sources.
An integrated circuit comprising a plurality of CMOS circuits connected in series with each other, said CMOS circuits being connected between a first reference line and second reference line, a first transistor being provided between at least one of said CMOS circuits and said first reference line and a second transistor being provided between at least one of said CMOS circuits and said second reference line, wherein first capacitive means is provided in parallel with said first transistor and second capacitive means is provided in parallel with said second transistor such that, in use, said first and second transistors operate as respective current sources.
A method of fabricating an integrated circuit, the method comprising forming a plurality of CMOS circuits in a substrate, connecting said CMOS circuits in series with each other and connecting each circuit between a first reference line and a second reference line, providing a first transistor between at least one of said circuits and said first reference line and providing a second transistor between at least one of said circuits and said second reference line, and providing first capacitive means in parallel with said first transistor and providing second capacitive means in parallel with said second transistor such that, in use, said first and second transistors operate as first and second respective current sources.
Dependencies are inferred from the claim text.