Low leakage and data retention circuitry

An integrated circuit comprising:

• two power supply terminals for powering of the integrated circuit, said power supply terminals including a Vdd positive supply terminal and a Vss ground terminal together defining a range of logic levels;
• cells in series with a sleep transistor electrically connected to one of said power supply terminals, each of said cells being either a logic gate or a storage cell;
• generator circuitry configured to generate a variable voltage outside said range of logic levels;
• and
• additional circuitry configured to apply, in a power down mode, said variable voltage to said sleep transistor.

A power management method comprising:

• operating an integrated circuit having cells, each of the cells being a either a logic gate or a storage cell, said cells being in series with a sleep transistor electrically connected to a either a Vdd positive supply terminal or a Vss ground terminal, the Vdd positive supply terminal and the Vss ground terminal together defining a range of logic levels, and the operating of the integrated circuit including:
• generating a variable voltage outside said range of logic levels;
• and
• applying, in a power down mode, said variable voltage to the sleep transistor.