High capacitive load and noise tolerant system and method for controlling the drive strength of output drivers in integrated circuit devices
AssigneeProMOS Technologies PTE.LTD.
InventorSteve Eaton
Life of this patent
Estimating the term…
Abstract
An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver, wherein the control signals are generated simultaneously, except for two the strongest driver transistors.
Claims21
An output driver calibration circuit comprising:
- a programmable drive strength output pullup driver comprising a strongest transistor and a plurality of other transistors;
- a programmable drive strength output pulldown driver comprising a strongest transistor and a plurality of other transistors;
- and
- a calibration circuit for generating a plurality of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver,
- wherein the control signals are generated simultaneously, except for the strongest driver transistors.
An output driver calibration circuit comprising:
- an output impedance node;
- an N-channel block of transistors;
- a P-channel block of transistors;
- a first current mirror having a first input coupled to the output impedance node, a first output coupled to the N-channel block of transistors, and a second output;
- a second, parallel, current mirror having a first input coupled to the output impedance node, a first output coupled to the N-channel block of transistors, and a second output;
- and
- a third current mirror having an input coupled to the second outputs of the first and second current mirrors, and an output coupled to the P-channel block of transistors.
An output driver calibration circuit comprising:
- an output impedance node;
- an N-channel block of transistors;
- a P-channel block of transistors;
- a first current mirror having a first input coupled to the output impedance node, a first output coupled to the P-channel block of transistors, and a second output;
- a second, parallel, current mirror having a first input coupled to the output impedance node, a first output coupled to the P-channel block of transistors, and a second output;
- and
- a third current mirror having an input coupled to the second outputs of the first and second current mirrors, and an output coupled to the N-channel block of transistors.
An output driver calibration circuit comprising:
- a programmable drive strength output pullup driver comprising a strongest transistor and a plurality of other transistors;
- a programmable drive strength output pulldown driver comprising a strongest transistor and a plurality of other transistors;
- and
- a calibration circuit for generating a plurality of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver,
- wherein the control signals are generated simultaneously for at least one set of drivers but not for all drivers.
Dependencies are inferred from the claim text.