Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsSHINYA SUZUKI, Kazuhisa Higuchi
Life of this patent
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Abstract
Signal lines which provide electric connections from an internal circuit formed on a main surface of a semiconductor chip and including, for example, MIS transistor to protective elements constituted by, for example, diodes are drawn out from outlet ports formed on wiring lines disposed between the protective elements, and a signal line region occupied by the signal lines is provided over the protective elements and under electrode pads. A wiring region on the main surface of the semiconductor chip can be enlarged without increasing the chip area.
Claims17
A semiconductor device comprising:
- a semiconductor substrate of a rectangular shape having a first long side, a second long side opposed to the first long side, a first short side and a second short side opposed to the first short side;
- a plurality of first bumps formed over the semiconductor substrate and arranged along the first long side;
- a plurality of second bumps formed over the semiconductor substrate and arranged along the second long side;
- a plurality of wirings formed under the first bumps;
- and
- a plurality of dummy wirings formed under the first bumps and formed at the same layer as the wirings,
- wherein the dummy wirings are arranged such that the number of dummy wirings arranged near the first or second short sides is larger than the number of dummy wirings arranged near a central portion of the first long side.
A semiconductor device comprising:
- a semiconductor substrate of a rectangular shape having a first long side, a second long side opposed to the first long side, a first short side and a second short side opposed to the first short side;
- a plurality of first bumps formed over the semiconductor substrate and arranged along the first long side;
- a plurality of second bumps formed over the semiconductor substrate and arranged along the second long side;
- a plurality of wirings formed under the first bumps;
- a plurality of dummy wirings formed under the first bumps and formed at the same layer as the wirings;
- a plurality of protective elements formed on the semiconductor substrate, electrically connected to the wirings and arranged under the first bumps in a plan view,
- wherein the dummy wirings are not electrically connected to protective elements, and
- wherein dummy wirings are arranged such that the number of dummy wirings arranged near the first or second short sides is larger than the number of dummy wirings arranged near a central portion of the first long side.
Dependencies are inferred from the claim text.