Semiconductor device
AssigneeSeiko Instruments Inc.
InventorsHideo Yoshino, Hirofumi Harada, Jun Osanai
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed.
Claims14
A semiconductor device, comprising a reference voltage generating circuit, the reference voltage generating circuit comprising:
- an enhancement type metal-oxide-semiconductor (MOS) transistor formed in a first well having a first impurity concentration;
- and
- a depletion type MOS transistor formed in a second well having a second impurity concentration different from the first impurity concentration of the first well.
A semiconductor device, comprising:
- an enhancement type MOS transistor formed in a first well having a first impurity concentration;
- and
- a depletion type MOS transistor formed in a second well having a second impurity concentration different from the first impurity concentration of the first well.
Dependencies are inferred from the claim text.